CSCE 2214 Computer Organization (Fall 2021)

 

Course Description: Students will study the design and implementation of a standard Reduced Instruction Set Computer (RISC) and memory hierarchy. Detailed analysis of instruction set encodings and efficient pipelined implementation of the instruction set including data and control hazards introduced by pipelining instruction execution. The Laboratory component allows students to apply classroom theory by designing and implementing a complete working pipelined CPU, and evaluating cache organizations through a simulator.
   
Credit hours: 4
   
Meetings:

Lecture: M/W/F 11:50 am - 12:40 pm, SCEN 101

   
Instructor:

Miaoqing Huang

Office: JBHT 526

Phone: 479-575-7578

Email: mqhuang AT uark.edu

   
Office Hours:

Monday  9:30 - 10:30 am, Wednesday 1:30 - 2:30 pm

   
TA: Seth Basler, Apoorva Bisht, Luke Waind
Office: JBHT 434
Office hours: Seth: T/Th 11 am - 12 pm; Apoorva: T/Th 11 am - 12 pm; Luke: Tuesdays 11 am - 12 pm.
Email: msbasler@uark.edu, abisht@uark.edu, ldwaind@uark.edu
Lab website: Blackboard (learn.uark.edu)
   
Textbook:

David A. Patterson and John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Fifth Edition, Morgan Kaufmann, October 2013, ISBN: 978-0124077263

   
Download: MIPS-32 Instruction Set Detailed Explanation, MIPS-32 Reference Card, Prefixes
   
Syllabus: Download here.

 

 

 

Class Schedule: (subject to change)

 

 

Week

Date

Content

Lecture

Note

1

8/23  Course introduction and syllabus    
8/25  Number Representations & Operations Lecture_0  
8/27  Computer Classification, Components, & Trends   Lecture_1.1  
2 8/30      
9/1      
9/3  Computer Performance   Lecture_1.2  
3 9/6     Labor Day
9/8  Instructions: Introduction   Lecture_2.1  
9/10  Instructions: Representation Lecture_2.2  
4 9/13      
9/15      
9/17      
5 9/20  Instructions: Memory Operations Lecture_2.3  
9/22      
9/24  Instructions: Logic Operations Lecture_2.4  
6 9/27  Instructions: Branch and Jump Instructions Lecture_2.5  
9/29      
10/1      
7 10/4  Instructions: Procedure Call Lecture_2.6  
10/6      
10/8      
8 10/11      
10/13      
10/15      
9 10/18      
10/20  Processor: Introduction & Logic Design Conventions Lecture_3.1  
10/22   Midterm Exam 1    
10 10/25     Fall Break
10/27  Processor: Building a Datapath with Control Lecture_3.2  
10/29      
11 11/1  Processor: Single-cycle Implementation Lecture_3.3  
11/3  Processor: Pipelining Datapath and Control Lecture_3.4  
11/5      
12 11/8  Processor: Data Hazards Lecture_3.5  
11/10      
11/12  Processor: Control Hazards Lecture_3.6  
13 11/15      
11/17  Memory Hierarchy: Introduction  Lecture_4.1  
11/19  Memory Hierarchy: Cache Basics  Lecture_4.2  
14 11/22   Midterm Exam 2    
11/24     Thanksgiving
11/26    
15 11/29      
12/1      
12/3      
16 12/6      
12/8      
12/10      Dead Day, no class
17 12/x Final Exam    

 

 

Lab Schedule: (subject to change)

 

Week

  Lab

    1

   Lab 1
   2    Lab 1 
   3    No Lab
   4    Lab 2 
   5    Lab 3
   6
   7
   8    Lab 4
   9    Lab 5
   10    No Lab
   11    Lab 6
   12    Lab 7
   13    Lab 8
   14    No Lab
   15    Lab 9
   16    No Lab

 

 

Lecture Slides: (subject to change)

 

 

Lecture

Content

Download

Coverage

Lecture_0  Number Representations & Operations Link  Textbook Chapter 2.4 
Lecture_1.1  Computer Classification, Components, & Trends   Link  Textbook Chapters 1.1, 1.4, 1.7, 1.8  
Lecture_1.2  Computer Performance   Link  Textbook Chapters 1.3, 1.6
Lecture_2.1  Instructions: Introduction   Link  Textbook Chapters 2.1, 2.2, 2.3  
Lecture_2.2  Instructions: Representation Link  Textbook Chapter 2.5 
Lecture_2.3  Instructions: Memory Operations Link  Textbook Chapter 2.5 
Lecture_2.4  Instructions: Logic Operations Link  Textbook Chapter 2.6 
Lecture_2.5  Instructions: Branch and Jump Instructions Link  Textbook Chapter 2.7 
Lecture_2.6  Instructions: Procedure Call Link  Textbook Chapter 2.8 
Lecture_3.1  Processor: Introduction & Logic Design Conventions Link  Textbook Chapters 4.1, 4.2
Lecture_3.2  Processor: Building a Datapath with Control Link  Textbook Chapters 4.3, 4.4
Lecture_3.3  Processor: Single-cycle Implementation Link  Textbook Chapter 4.4
Lecture_3.4  Processor: Pipelining Datapath and Control Link  Textbook Chapter 4.5, 4.6
Lecture_3.5  Processor: Data Hazards Link  Textbook Chapter 4.7
Lecture_3.6  Processor: Control Hazards Link  Textbook Chapter 4.8
Lecture_4.1  Memory Hierarchy: Introduction  Link  Textbook Chapter 5.1 
Lecture_4.2  Memory Hierarchy: Cache Basics  Link  Textbook Chapter 5.3 
Lecture_4.3  Memory Hierarchy: Improving Cache Performance  Link  Textbook Chapter 5.4 
Lecture_4.4  Memory Hierarchy: Virtual Memory  Link  Textbook Chapter 5.7 

 

Homework:

 

    Visit Blackboard (learn.uark.edu) for questions and solutions.

 

Exam:

 

    Visit Blackboard (learn.uark.edu) for reference exams and solutions.   

 

Grading:

 

    A: over 90% and the grade of final exam 75

    B: 80% - 89%

    C: 70% - 79%

    D: 60% - 69%

    F: below 60%

  

    Course tasks are weighed using the following scale:

 

    Midterm exams (2):     30%

    Final exam:                20%

    Homework:                 15%

    Lab Projects:              25% 

    Quizzes:                    10% 

 

 

Note: Most of the lecture slides are provided by the publisher of the required textbook. Part of the slides are borrowed from the slides prepared by Prof. Mary Jane Irwin with PSU.