DARPA Grant Received
Dr. Jia Di received $305,326 from the Defense Advanced Research Projects Agency (DARPA) with Drs. Scott Smith and Alan Mantooth in ELEG department to study ultra-low power asynchronous circuit design. Power consumption has become one of the most critical design challenges to digital IC designers. Circuits operating in subthreshold region, i.e., the supply voltage, VDD, is below the transistors' threshold voltages, Vt, are able to achieve very low power consumption. However, reducing VDD causes the delay to increase drastically.
To improve the circuit speed, threshold voltages need to be scaled down with VDD, which causes the leakage power to increase. Multi-threshold CMOS (MTCMOS) uses transistors with different threshold voltages. The logic blocks consist of low-Vt transistors for better speed in active mode, while high-Vt transistors are used to gate the power in sleep mode to reduce leakage. Unfortunately, the prevailing MTCMOS synchronous circuits have three major drawbacks - "sleep-transistor" sizing, storage element data loss, and sleep signal generation.
This project aims to solve these problems by utilizing delay-insensitive asynchronous logic. A number of prototype circuits will be designed in both synchronous and asynchronous logic and will be fabricated onto two ICs, which will be tested for evaluating the effectiveness and efficiency of the proposed method.
